1. Field of the Invention
The present invention relates to extremely low power voltage translator circuitry and, more particularly, to an ultra low power TTL-to-CMOS buffer.
2. Description of the Related Art
A voltage translator circuit is a level shifter that shifts voltages from one logic level to another logic level. A TTL-to-CMOS buffer, in particular, is a device that converts TTL logic levels into CMOS logic levels. With TTL logic levels, a logic high is represented by voltages that fall within a range from VIH (MIN) to VIH (MAX), such as +2.0V to VCC (e.g., +5.0V). In addition, a logic low is represented by voltages that fall within a range from VIL (MIN) to VIL (MAX), such as ground to +0.8V. On the other hand, with CMOS logic levels, a logic high is represented by VCC, and a logic low is represented by ground.
FIG. 1A shows a schematic diagram that illustrates a conventional TTL-to-CMOS buffer 100. As shown in FIG. 1A, TTL-to-CMOS buffer 100 includes a first inverter 110 and a second inverter 112 that is connected in series with first inverter 110. Inverter 110 is typically implemented as a standard inverter, while inverter 112 is typically implemented with a Schmitt trigger type of arrangement for good hysteresis characteristics.
FIG. 1B shows a schematic diagram that illustrates first inverter 110. As shown in FIG. 1B, inverter 110 includes a p-channel transistor P1 and an n-channel transistor N1. P-channel transistor P1 has a source connected to a power supply node PSN to receive a power supply voltage VCC, a drain connected to an output node NOUT, and a gate connected to an input node NIN. N-channel transistor N1 has a source connected to ground, a drain connected to the output node NOUT, and a gate connected to the input node NIN.
In operation, p-channel transistor P1 turns on and conducts when the source-to-drain voltage VSD is greater than zero (e.g., VSD greater than 0), and the gate-to-source voltage VGS is less than the threshold voltage VTP of the transistor (e.g., VGS less than VTP). N-channel transistor N1 turns on and conducts when the drain-to-source voltage VDS is greater than zero (e.g., VDS less than 0), and the gate-to-source voltage VGS is greater than the threshold voltage VTN of the transistor (e.g., VGS greater than VTN).
One of the advantages of inverter 110 is that when an input voltage VIN on the input node NIN is at CMOS levels, no current is dissipated. For example, when the input voltage VIN is at ground, p-channel transistor P1 is turned on and n-channel transistor N1 is turned off. Similarly, when the input voltage VIN is at VCC, p-channel transistor P1 is turned off and n-channel transistor N1 is turned on.
One of the disadvantages of inverter 110, however, is that when the input voltage VIN is at TTL levels, a substantial amount of current can be dissipated as transistors P1 and N1 are often both turned on. For example, when a logic high is represented by an input voltage VIN of +2.0V, the threshold voltage VTP is xe2x88x921.0V, the threshold voltage VTN is +0.7V, and VCC is +5.0V, both transistors P1 and N1 are turned on. (For transistor P1, VGS=2.0xe2x88x925=xe2x88x923.0. Since xe2x88x923.0V is less than the threshold voltage VTP of xe2x88x921.0V, transistor P1 is turned on. For transistor N1, VGS=2.0xe2x88x920=2.0. Since 2.0V is greater than the threshold voltage VTN of 0.7V, transistor N1 is turned on.)
Similarly, when a logic low is represented by an input voltage VIN of +0.8V, both transistors P1 and N1 are again turned on. (For transistor P1, VGS=0.8xe2x88x925=xe2x88x924.2. Since xe2x88x924.2V is less than the threshold voltage VTP of xe2x88x921.0V, transistor P1 is turned on. For transistor N1, VGS=0.8xe2x88x920=0.8. Since 0.8V is greater than the threshold voltage VTN of 0.7V, transistor N1 is turned on.)
Since transistors P1 and N1 can both be turned on at the same time, the strength of n-channel transistor N1 is typically set to insure that when the input voltage VIN is greater than VIH (MIN), n-channel transistor N1 overpowers p-channel transistor P1 so that the voltage on the output node NOUT is pulled down to ground. In addition, the strength of n-channel transistor N1 is also set to insure that when the input voltage VIN is less than VIL (MAX), p-channel transistor P1 overpowers n-channel transistor N1 and the voltage on the output node NOUT is pulled up to VCC.
In almost every conventional TTL-to-CMOS buffer or a level shifter, an inverter, with its input at one logic level, and its power supplies at another logic level, is present. In a TTL-to-CMOS buffer, since a substantial amount of current is dissipated when the input voltage VIN is at TTL levels and transistors P1 and N1 are both turned on, there is a need for an inverter that operates on TTL levels, and dissipates little or no current throughout the range of operation. This is also applicable for a generalized level shifter.
Conventionally, a substantial amount of current is dissipated when the voltage input to a TTL-to-CMOS buffer via an input inverter is at TTL levels. This is because the TTL levels turn on both the p-channel and n-channel transistors of the input inverter. The present invention reduces the amount of current dissipated at TTL levels by insuring that only one of the two transistors is on when the input voltage is at a TTL level. The present invention is also applicable in the case of other low power level shifter circuits.
A translator circuit in accordance with the present invention includes an inversion stage that outputs an inversion signal in response to an input signal. The inversion signal has a logic high equal to a first voltage which is less than an upper supply voltage, and a logic low equal to a second voltage which is greater than a lower supply voltage.
The circuit also includes a logic-low translation stage that outputs a translation signal in response to the inversion signal. The translation signal has a logic high equal to a second voltage which is less than the first voltage, and a logic low equal to the lower supply voltage. The circuit of the present invention further includes a logic-high translation stage that outputs an output signal in response to the translation signal. The output signal has a logic high equal to the upper supply voltage, and a logic low equal to the lower supply voltage.
The present invention also includes a method for operating a translator circuit. The method includes the step of outputting an inversion signal from an inversion stage in response to an input signal. The inversion signal has a logic high equal to a first voltage which is less than an upper supply voltage, and a logic low equal to a second voltage which is greater than a lower supply voltage.
The method also includes the step of outputting a translation signal from a logic-low translation stage in response to the inversion signal. The translation signal has a logic high equal to a second voltage which is less than the first voltage, and a logic low equal to the lower supply voltage. The method further includes the step of outputting an output signal from a logic-high translation stage in response to the translation signal. The output signal has a logic high equal to the upper supply voltage, and a logic low equal to the lower supply voltage.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.